SOFTWARE REQUIREMENT XILINX ISE DESIGN SUITE 10.1 VERSION
HARDWARE REQUIREMENT:
PERSONAL COMPUTER
SPARTAN 3E(XC3S100E)
BUSES
This is the way to do project practice simple for beginner to excellent learning from this blog . i can explain clearly about to do project in VLSI by using verilog coding WITH GOOD EXAMPLES
There are two ways i can give code for every module in hardware description lanuage (HDL) and similarly in verilog and system verilog also.
let we start from one way to go for another way for practice first and do more projects on it .
COMPUTATIONAL CIRCUITS AND SEQUENTIAL CIRCUITS
COMPUTATIONAL CIRCUITS
GATES
ADDERS
HALF ADDER
FULL ADDER
RIPPLE CARRY ADDER.
CARY LOOK AHEAD ADDER
MULTIPLEXER
(4X1)
(8X1)
(16X1)
DEMULTIPLEXERS
(1X4)
(1X8)
(1X16)
DECODER (2 TO 4)
(3 TO 8)
(4 TO 16)
SEQUENTIAL CIRCUITS
FLIP FLOPS
RS FLIP FLOPS
JK FLIP FLOPS
D FLIP FLOPS
T FLIP FLOPS
COUNTERS
4-BIT COUNTER
8-BIT COUNTER
DECADE COUNTER
UP/DOWN COUNTER
RING COUNTER
JHONSON COUNTER
REGISTERS
SHIFT REGISTER
SISO REGISTER
PIPO REGISTER
ALU
FAGA
ASIC
HARDWARE REQUIREMENT:
PERSONAL COMPUTER
SPARTAN 3E(XC3S100E)
BUSES
This is the way to do project practice simple for beginner to excellent learning from this blog . i can explain clearly about to do project in VLSI by using verilog coding WITH GOOD EXAMPLES
There are two ways i can give code for every module in hardware description lanuage (HDL) and similarly in verilog and system verilog also.
let we start from one way to go for another way for practice first and do more projects on it .
COMPUTATIONAL CIRCUITS AND SEQUENTIAL CIRCUITS
COMPUTATIONAL CIRCUITS
GATES
ADDERS
HALF ADDER
FULL ADDER
RIPPLE CARRY ADDER.
CARY LOOK AHEAD ADDER
MULTIPLEXER
(4X1)
(8X1)
(16X1)
DEMULTIPLEXERS
(1X4)
(1X8)
(1X16)
DECODER (2 TO 4)
(3 TO 8)
(4 TO 16)
SEQUENTIAL CIRCUITS
FLIP FLOPS
RS FLIP FLOPS
JK FLIP FLOPS
D FLIP FLOPS
T FLIP FLOPS
COUNTERS
4-BIT COUNTER
8-BIT COUNTER
DECADE COUNTER
UP/DOWN COUNTER
RING COUNTER
JHONSON COUNTER
REGISTERS
SHIFT REGISTER
SISO REGISTER
PIPO REGISTER
ALU
FAGA
ASIC
i am very clear to give full information about vlsi digital design in verilog and system verilog and hdl
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