VERILOG AND HDL DESIGN WITH FLOW CHART AND EXAMPLE

FPGA demonstrates good performance and logic capacity by exploiting parallelism. At present single FPGA platform can play multi-functions, including control, filter and system. FPGA design flow is a three-step process consisting of design entry, implementation, and verification stages, as shown in Fig 2.1.The full design flow is an iterative process of entering, implementing, and verifying the design until it is correct and complete.

Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction

            Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway Design Automation) in 1985. The company was privately held at that time by Dr. Prabhu  Goel, the inventor of the PODEM test generation algorithm. Verilog HDL was designed by Phil Moorby, who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems. Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally acquired by Cadence Design Systems, San Jose, CA in 1989.

              Verilog was invented as simulation language. Use of Verilog for synthesis was a complete afterthought. Rumors abound that there were merger discussions between Gateway and Synopsys in the early days, where neither gave the other much chance of success.

VERILOG is fully simulatable, but not fully synthesizable. There are several VERILOG constructs that do not have valid representation in a digital circuit. Other constructs do, in theory, have a representation in a digital circuit, but cannot be reproduced with guaranteed accuracy. Delay time modeling in VERILOG is an example. State-of-the-art synthesis algorithms can optimize Register Transfer Level (RTL) circuit descriptions and target a specific technology. Scheduling and allocation algorithms, which perform circuit optimization at a very high and abstract level, are not yet robust enough for general circuit applications. Therefore, the result of synthesizing a VERILOG description depends on the style of VERILOG that is used.

 In Verilog minute errors won’t popup during the compilation time. It will pop up at the time of synthesis only. The Verilog language is still rooted in its native interpretative mode. Compilation is a means of speeding up simulation, but has not changed the original nature of the language. As a result care must be taken with both the compilation order of code written in a single file and the compilation order of multiple files. Simulation results can change by simply changing the order of compilation.

There is no equivalent to the generate statement in Verilog. Signals representing objects of different bits widths may be assigned to each other. The signal representing the smaller number of bits is automatically padded out to that of the larger number of bits, and is independent of whether it is the assigned signal or not. Unused bits will be automatically optimized away during the synthesis process. This has the advantage of not needing to model quite so explicitly as in VHDL, but does mean unintended modeling errors will not be identified by an analyzer.

The standard design flow comprises the following steps:

Ø  Design Entry and Synthesis: In this step of the design flow, design is created using a, a hardware description language (HDL) for text-based entry. Xilinx Synthesis Technology (XST) GUI can be used to synthesize the HDL file into an NGC file.

Ø  Design Implementation: By implementing to a specific Xilinx architecture, the logical design file format, such as EDIF, that is created in the design entry and synthesis stage is converted into a physical file format. The physical information is contained in the native circuit description (NCD) file for FPGAs Then bit stream file is created from these files and optionally a PROM or EPROM is programmed for subsequent programming of Xilinx device.

Ø  Design Verification: Using a gate-level simulator or cable, it is ensured that the design meets timing requirements and functions properly.

To define the behavior of the FPGA, the user provides a hardware description language (HDL) or a schematic design. The HDL form is more suited to work with large structures because it's possible to just specify them numerically rather than having to draw every piece by hand. However, schematic entry can allow for easier visualization of a design. Then, using an electronic design automation tool, a technology-mapped net list is generated. The net list can then be fitted to the actual FPGA architecture using a process called place-and-route, usually performed by the FPGA Company’s proprietary place-and-route software.

The various steps involved in the design flow are as follows:

1) The design

2] Processes and properties

3] Synthesize options

4] Write Timing Constraints

5) Timing simulation of the design after post PAR.

6) Static timing analysis.

7) Configuring the device by bit generation.

Ø  Design entry

The first step in implementing the design is to create the HDL code based on design criteria. To support these instantiations we need to include UNISIM library and compile all design libraries before performing the functional simulation. The constraints (timing and area constraints) can also be included during the design entry. Xilinx accepts the constraints in the form of user constraint (UCF) file.

Ø  Functional Simulation

This step deals with the verification of the functionality of the written source code. ISE provides its own ISE simulator and also allows for the integration with other tools such as ModelSim. This project uses ModelSim for the ise. Functional simulation can take place at the earliest stages of the design flow. Because timing information for the implemented design is not available at this stage, the simulator tests the logic in the design using unit delays.

Ø  Synthesizing and Optimizing

In this stage behavioral information in the HDL file is translated into a fed into the Xilinx software program called NGD Build, which produces a logical native generic database (NGD) file.

Ø  Design implementation

In this stage, The MAP program maps a logical design to a Xilinx FPGA. The input to MAP is an NGD file, which is generated using the NGD Build Xilinx primitives. The NGD file also contains any number of NMC (macro library) files, each of which contains the definition of a physical macro. MAP first performs a logical DRC (Design Rule Check) on the design in the NGD file. MAP then maps the design logic to the components (logic cells, I/O cells, and other components) in the target Xilinx FPGA The output from MAP is an NCD (Native Circuit Description) file, and PCF (Physical constraint file).

Ø  Timing simulation after post PAR

Timing simulation at this stage verifies that the design runs at the desired speed for the device under worst-case conditions. This process is performed after the design. It can also determine whether or not the design contains set-up or hold violations. In most of the designs the same test bench can be used to simulate at this stage.

Ø  Static timing analysis

Static timing analysis is best for quick timing checks of a design after it is placed and routed. It also allows you to determine path delays in your design. Following are the two major goals of static timing analysis:

• Timing verification:-This is verifying that the design meets your timing constraints.

           • Reporting:-This is enumerating input constraint violations and placing them into an accessible TRACE are .ncd file and .pcf from PAR .and the output file is a .twr file.

Ø  Configuring the device by BitGen

After the design is completely routed, it is necessary to configure the device so that it the configuration information from the NCD file that defines the internal logic and interconnections of the FPGA, plus device-specific information from other files associated with the target device. The binary data in the BIT file is then downloaded into the FPGAs memory cells, or it is used to create a PROM file.

2.6.1        Processes and properties

Processes and properties enable the interaction of our design with the functionality available in the ISE™ suite of tools.

Ø  Processes

Processes are the functions listed hierarchically in the Processes window. They perform functions from the start to the end of the design flow.

Ø  Properties

Process properties are accessible from the right-click menu for select processes. They enable us to customize the parameters used by the process. Process properties are set at synthesis and implementation phase.

2.6.2        Synthesize options:

The following properties apply to the Synthesize properties .using the Xilinx® Synthesis Technology (XST) synthesis tool.

The drop-down list.

Speed:-Optimizes the design for speed by reducing the levels of logic.

Area:-property is set to Speed.

Ø  Optimization Effort

Specifies the synthesis optimization effort level.

Select an option from the drop-down list.

Normal: - Optimizes the design using minimization and algebraic factoring    algorithms.

High: - Performs additional optimizations that are tuned to the selected device

Normal: - This project aims at Timing performance and was selected HIGH effort level.

Ø  Power Reduction

When set to is set to No (checkbox is blank).

Ø  Use Synthesis Constraints File: Specifies whether or not to use the constraints file entered in the previous property. By default, this constraints file is used (property checkbox is checked).

Ø  Keep Hierarchy: Specifies whether or not the corresponding design unit should be preserved and not merged with the rest of the design. You can specify Yes, No and Soft property from no to yes give me almost doubles the speed.

Ø  Global Optimization Goal: Specifies the global timing optimization goal Select Optimizes the maximum delay from input pad to clock, either for a specific clock or for an entire design. Offset Out After Optimizes the maximum delay from clock to output pad, either for a specific is set to All Clock Nets.

Ø  Generate RTL Schematic: Generates a pre-optimization RTL schematic of the design. Values for this property are Yes, No, and only. Only stops the synthesis process before optimization, after the RTL schematic has been generated. The default value is yes.

Ø  Read Cores: Specifies whether or not black box core are read for timing and area estimation (checkbox is blank), cores are not read. By default, this property is set to True (checkbox is checked).

2.6.3        Write Timing Constraints (FPGA only)

 Specifies whether or not to place timing constraints in the NGC file. The timing constraints in the NGC file will be used during place and route, as well as synthesis optimization. By default, this property is set to False (checkbox is blank).

Ø  Slice Utilization Ratio: Specifies resource management by entering -1 here.

Ø  LUT-FF Pairs Utilization Ratio: Specifies the area size (in %) that XST will not exceed during timing optimization. If the resource management by entering-1 here.

Ø  BRAM Utilization Ratio

Specifies the number of BRAM blocks (in %) that XST will not exceed during synthesis. The default percentage is 100%. You can disable automatic BRAM resource management by entering -1 here.

2.6.4        Implementation Options

Perform Timing-Driven Packing and Placement Specifies whether or not to give priority to timing critical paths during packing in the Map Process. User-generated timing constraints are used to result is a completely placed design, and the design is ready for routing. If Timing-Driven Packing and Placement is selected in the absence of user timing constraints, the tools will automatically generate and dynamically adjust timing constraints for all internal clocks. This feature is referred to as “achieve. Instead it is a “balance” of performance between all clocks in the design. By default, this property is set to False (checkbox is blank).This project aims at speed and this option is selected.

Ø  Map Effort Level: Note:  Available only when Perform Timing-Driven Packing and Placement is set to True (checkbox is checked). Specifies the effort level to apply to the Map process. The effort level controls the amount of time used for packing and placement by selecting a more or less CPU-intensive algorithm for placement. Select an Gives the longest run time with the best mapping results. Appropriate for a more complex design. By default, this property is set to Medium. As this project is a complex design the option high is selected.

Ø  Extra Effort: Map is applied. Normal R-uns until timing constraints are met unless they are found to be impossible to meet. This option focuses on meeting timing constraints. This project has a timing constraint of 100 ns; to meet this option Normal is selected.

2.6.5        Combinatorial Logic Optimization: Specifies whether or not to run a process that revisits the combinatorial design. This project aims to meet timing constraint and this option is selected.

2.6.6        Optimization Strategy (Cover Mode)

Specifies the criteria used during the "cover" phase of MAP. In the "cover" phase, MAP assigns the logic to CLB function generators (LUTs). Select an option from the drop-down list.

Ø  Area: Select Area to make reducing the number of LUTs (and therefore the number of CLBs) the highest priority.

Ø  Speed: Select Speed to make reducing the number of levels of LUTS (the number of LUTs a path passes through) the highest priority. This setting makes it the area setting), and in some cases the increase may be large.

Ø  Balanced: Select Balanced to balance two priorities; reducing the number of LUTs and reducing the number of levels of LUTs. The Balanced option produces results

Ø  Optimization: By default, this property is set to Area. To meet timing constraints this project selected the option of speed.

2.6.7        PAR properties

Ø  Place and Route Effort Level (Overall)

Specifies CPU-intensive algorithm for placement and routing. You can set the overall level from Standard (fastest run time) to High (best results). By default, this property is set at Standard. To meet the timing constraint HIGH is selected for this project.