VERILOG CODE WITH EXAMPLE FOR PRACTICE

VERILOG CODE WITH EXAMPLE FOR PRACTICE 

BASIC MODULE CODE

// module_tff.v

//library ieee;
//use ieee.std_logic_1164.all;
//use ieee.numeric_std.all;

module ripple_carry_counter(q,clk,reset);
output [3:0] q;
input clk,reset;
T_FF tff0(q[0],clk,reset);
T_FF tff1(q[1],q[0],reset);
T_FF tff2(q[2],q[1],reset);
T_FF tff3(q[3],q[2],reset);
endmodule

module T_FF(q,clk,reset);
output q;
input clk,reset;
wire d;
D_FF dff0(q,d,clk,reset);
not n1(d,q);
endmodule

module D_FF(q,d,clk,reset);
output q;
input d,clk,reset;
reg q;
always @(posedge reset or negedge clk)
if(reset)
q<=1'b0;
else
q<=d;
endmodule

FULL ADDER

module fulladd(sum,c_out,a,b,c_in);
output sum,c_out;
input a,b,c_in;

wire s1,c1,s2;

xor x1(s1,a,b);
and a1(c1,a,b);
xor x2(sum,s1,c_in);
and a2(s2,s1,c_in);
xor x3(c_out,s2,c1);

endmodule


module fulladd4(sum,c_out,a,b,c_in);

output [3:0]sum;
output c_out;
input [3:0]a,b;
input c_in;

wire c1,c2,c3;

fulladd fa0(sum[0],c1,a[0],b[0],c_in);
fulladd fa1(sum[1],c2,a[1],b[1],c1);
fulladd fa2(sum[2],c3,a[2],b[2],c2);
fulladd fa3(sum[3],c_out,a[3],b[3],c3);

endmodule

  

  RIPPLE CARRY COUNTER

// ripple_carry_counter.v
module ripple_carry_counter(q,clk,reset);
output [3:0]q;
input clk,reset;


T_FF tff0(q[0],clk,reset);
T_FF tff1(q[1],q[0],reset);
T_FF tff2(q[2],q[1],reset);
T_FF tff3(q[3],q[2],reset);


endmodule


module T_FF(q,clk,reset);
output q;
input clk,reset;
wire d;


D_FF dff0(q,d,clk,reset);
not n1(d,q);
endmodule


module D_FF(q,d,clk,reset);
output q;
input d,clk,reset;
reg q;


always @(posedge reset or negedge clk)
if (reset)
q<=1'b0;
else
q<=d;
endmodule

SHIFT REGISTER

module shift_register(clk,si,po);
input clk,si;
output [7:0]po;
reg [7:0]temp;

always @(posedge clk)
begin
temp <= {temp[6:0],si};
end
assign po = temp;
endmodule

SR-LATCH

// sr_latch.v

module sr_latch(q,qbar,sbar,rbar);

output q,qbar;

input sbar,rbar;

nand n1(q,sbar,qbar);

nand n2(qbar,rbar,q);

endmodule

MULTIPLEXER

 module mux4_to_1(out,i0,i1,i2,i3,s0,s1);

  

  output out;

  input i0,i1,i2,i3;

  input s1,s0;

  

  wire s1n,s0n;

  wire y0,y1,y2,y3;

  

  not n1(s1n,s1);

  not n0(s0n,s0);

  

  and a0(y0,i0,s1n,s0n);

  and a1(y1,i1,s1n,s0);

  and a2(y2,i2,s1,s0n);

  and a3(y3,i3,s1,s0);

  or o1(out,y0,y1,y2,y3);

  

endmodule